[ 0.000] KHUSH-OS v1.0 :: rtl-core bring-up
[ 0.112] loading toolchain ........ OK (verilator, yosys, nextpnr)
[ 0.240] target device ........... XC7S25 / SCL 0.8um
[ 0.391] location ................ Mumbai, IN
[ 0.512] verification pipeline ... 7 agents online
[ 0.640] timing closure .......... tracking
[ 0.771] status ................. ready for silicon

FPGA & RTL Design Engineer

Khush Patil.
Building silicon for AI acceleration.

I design and verify digital hardware that moves data faster and closes timing cleaner. Currently an avionics research engineer on space-grade electronics and propulsion, with a focus on FPGA datapaths, automated RTL verification, and open-source silicon tooling.

LocationMumbai, Maharashtra

EmployerManastu Space Technologies

FocusFPGA / RTL / Verification

NextMSECE, Purdue (Fall 2026)

View projects Get in touch

100MHz

Board clock resource

14.6K

6-input LUTs (XC7S25)

80DSP

DSP slices (XC7S25)

202.5KB

Block RAM (XC7S25)

About

// profile

Hardware engineer, end to end

I work from the RTL up: architecture, implementation, timing, and the verification that proves it works. My background spans space-grade avionics, where failure is not an option, and open FPGA toolchains, where I help make the tools better for everyone.

// current

Where I'm pointed

Hardware acceleration for machine learning workloads: streaming datapaths, DMA-heavy pipelines, and verification flows that cut regression time without cutting coverage. Pursuing a master's in ECE at Purdue (PMP Implementation Track), enrollment deferred to Fall 2026.

Skills & stack

// design

RTL & architecture

SystemVerilogVerilogVHDL PipeliningCDCFSM designStreaming datapaths

// verification

Verify & prove

Functional coverageConstrained-randomAssertions (SVA) VerilatorRegression automationPython

// implementation

Synthesis & closure

Timing closureYosysnextpnrVivado OpenLaneConstraints (XDC/SDC)

// protocols

Interfaces

AXI4 / AXI-StreamPCIeSPII2C UARTDMA

// platforms

Devices & boards

Xilinx 7-seriesArty S7-25SCL 0.8um PDK 65C02 core portSpace-grade electronics

// tooling

Flow & infra

GitLinuxMake / CMake TclBashOpen-source EDA

Experience

Manastu Space TechnologiesMumbai, IN
Present

Avionics Research Engineer

Design and bring-up of FPGA-based avionics and propulsion control electronics for space-grade hardware.
Own RTL implementation, timing closure, and board-level verification across the flight electronics stack.
Build automated verification flows that reduce regression turnaround and tighten coverage closure.

FPGARTLTiming closureAvionicsPropulsion

Open-source silicon & FPGAOngoing

Toolchain & PDK contributor

Device model work for Arty S7-25 (XC7S25) across the openXC7 ecosystem, spanning database, place-and-route, and tooling.
Open-source 0.8um CP8D PDK with a 65C02 core port and synthesis findings fed back to the flow.

openXC7nextpnrOpenLanePDK

Projects

Vyom 2U CubeSat (Mission Adyanta)

Flight hw

avionics / propulsion / POEM-4

Avionics and propulsion electronics for a 2U CubeSat, from board-level design through integration and test.

DOMAIN Space-grade avionics
SCOPE Propulsion control and power path

AvionicsPropulsionCubeSat

RTL Verification Automation

Production

multi-agent verification pipeline

A seven-agent orchestrated pipeline that generates tests, runs regressions, and triages coverage gaps for FPGA RTL.

-75 to 85% verification cycles

CoverageSystemVerilogPythonRegression

SCL 0.8um CP8D Open PDK

Open source

scl_cp8d / OpenLane 1 / 5V

Open-source 5V process design kit for the SCL 0.8um node, validated through a 65C02 core port and synthesis flow runs.

PDKOpenLane65C02Synthesis

XC7S25 openXC7 Support